Title
Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture
Abstract
This paper presents an improved cluster-based Mesh architecture. This architecture has a depopulated intra-cluster interconnect, and presents a new hierarchical topology for the switch box which unifies a downward and an upward unidirectional networks. Experimental results of 20 MCNC benchmarks show that density is improved and interconnect area requirement is reduced by 42 % compared to the cluster-based VPR architecture.
Year
DOI
Venue
2013
10.1109/ReConFig.2013.6732282
ReConFig
Keywords
Field
DocType
field programmable gate arrays
Fpga interconnect,Architecture,Switch box,Interconnect topology,Computer science,Pattern clustering,Parallel computing,Field-programmable gate array,Fpga architecture,Interconnection
Conference
ISSN
ISBN
Citations 
2325-6532
978-1-4799-2078-5
3
PageRank 
References 
Authors
0.41
6
5
Name
Order
Citations
PageRank
Emna Amouri1397.83
Adrien Blanchardon261.16
Roselyne Chotin-Avot3319.43
Habib Mehrez420039.21
Zied Marrakchi515228.68