Name
Abstract | ||
|---|---|---|
The reliability of networks-on-chip (NoC) is threatened by low yield and device wearout in aggressively scaled technology nodes. We propose ReliNoC, a network-on-chip architecture which can withstand failures, while maintaining not only basic connectivity, but also quality-of-service support based on packet priorities. Our network leverages a dual physical channel switch architecture which removes the control overhead of virtual channels (VCs) and utilizes the inherent redundancy within the 2-channel switch to provide spares for faulty elements. Experimental results show that ReliNoC provides 1.5 to 3 times better network physical connectivity in presence of several faults, and reduces the latency of both high and low priority traffic by 30 to 50%, compared to a traditional VC architecture. Moreover, it can tolerate up to 50 faults within an 8×8 mesh at only 10 and 40% latency overhead on control and data packets for PARSEC traces. Synthesis results show that our reliable architecture incurs only 13% area overhead on the baseline 2-channel switch. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/DATE.2011.5763112 | Design, Automation & Test in Europe Conference & Exhibition |
Keywords | Field | DocType |
network-on-chip,quality of service,telecommunication network reliability,PARSEC traces,ReliNoC,networks-on-chip,priority-based on-chip communication,quality-of-service,reliable network,virtual channels | Parsec,Latency (engineering),Computer science,Network packet,Network on a chip,Computer network,Communication channel,Quality of service,Real-time computing,Redundancy (engineering),Fault tolerance,Embedded system | Conference |
ISSN | ISBN | Citations |
1530-1591 | 978-1-61284-208-0 | 20 |
PageRank | References | Authors |
0.76 | 21 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohammad Reza Kakoee | 1 | 72 | 3.99 |
| Valeria Bertacco | 2 | 1365 | 86.93 |
| Luca Benini | 3 | 13116 | 1188.49 |