Name
Abstract | ||
|---|---|---|
Process variations in advanced CMOS nodes limit the benefits of scaling for analog designs. In the presence of increasing random intra-die variations, mismatch becomes a significant design challenge for circuits such as comparators. In this paper we describe and demonstrate the details of a statistical element selection (SES) methodology that relies on the combinatorial growth of subsets of selectable circuit elements (e.g., input transistors in a comparator) to provide redundancy for post-manufacturing calibration of specifications (e.g., offset). A test chip consisting of an array of digitally calibrated comparators with built-in combinatorial redundancy was manufactured in 65 nm bulk CMOS. Over 99.5% of the comparators satisfy the given offset specification compared to 15% for Pelgrom-type sizing. A second test chip in the same process consists of an 8-bit, 1.5 GS/s flash ADC and achieves 37 db SNDR at low frequencies. The total power is 35 mW, 20 mW in the S&H and 15 mW in the ADC core. The figure of merit is 0.42 pJ/conv. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/JSSC.2011.2157255 | Solid-State Circuits, IEEE Journal of |
Keywords | Field | DocType |
CMOS analogue integrated circuits,CMOS logic circuits,analogue-digital conversion,built-in self test,calibration,combinational circuits,comparators (circuits),integrated circuit design,integrated circuit testing,redundancy,CMOS node process variation,Pelgrom-type sizing,SES methodology,analog design scaling,analog-to-digital converter,built-in combinatorial redundancy,circuit design,digitally calibrated comparator array,flash ADC,offset calibration,post-manufacturing calibration,random intra-die variation,size 65 nm,statistical element selection methodology,test chip,word length 8 bit,ADC,analog-to-digital converter,calibration,combinatorial redundancy,comparator,flash ADC,statistical element selection | Comparator,Computer science,CMOS,Flash ADC,Electronic engineering,Integrated circuit design,Redundancy (engineering),Electronic circuit,Offset (computer science),Built-in self-test | Journal |
Volume | Issue | ISSN |
46 | 8 | 0018-9200 |
Citations | PageRank | References |
10 | 0.79 | 27 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gökçe Keskin | 1 | 38 | 5.26 |
| Jonathan Proesel | 2 | 10 | 0.79 |
| Plouchart, J.-O. | 3 | 31 | 5.54 |
| Lawrence T. Pileggi | 4 | 1886 | 204.82 |