Name
Abstract | ||
|---|---|---|
This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TCAD.2014.2323216 | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions |
Keywords | DocType | Volume |
CMOS integrated circuits,MOSFET,automatic test pattern generation,failure analysis,integrated circuit testing,CMOS-based designs,FinFET technologies,automatic test pattern generation,cell-aware test,defect-oriented CAT fault model generation,failure analysis,transistor-level test,Automatic test pattern generation,FinFET test,cell-aware test,defect-based test,defective parts,design for testability,failure analysis,logic testing,test data compression,transistor-level test | Journal | 33 |
Issue | ISSN | Citations |
9 | 0278-0070 | 39 |
PageRank | References | Authors |
2.06 | 12 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hapke, F. | 1 | 39 | 2.06 |
| Redemund, W. | 2 | 39 | 2.06 |
| Glowatz, A. | 3 | 125 | 5.56 |
| J. Rajski | 4 | 985 | 63.36 |