Name
Abstract | ||
|---|---|---|
Programmable Graphics Processing Unit (GPU) has emerged as a powerful parallel processing architecture for various applications requiring a large amount of CPU cycles. In this paper, we study the feasibility for using this architecture for image halftoning, in particular implementing computationally intensive neighborhood halftoning algorithms such as error diffusion and Direct Binary Search (DBS). We show that it is possible to deliver very high performance even for high speed printers. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISCAS.2011.5937866 | Circuits and Systems |
Keywords | Field | DocType |
graphics processing units,image processing,parallel architectures,printers,CPU cycles,GPU-enabled parallel processing,computationally intensive neighborhood halftoning algorithms,direct binary search,error diffusion,high speed printers,image halftoning applications,parallel processing architecture,programmable graphics processing unit | Kernel (linear algebra),Computer science,Error diffusion,Parallel processing,Image processing,Pixel,Binary search algorithm,Computer hardware,Graphics processing unit,Instruction cycle | Conference |
ISSN | ISBN | Citations |
0271-4302 E-ISBN : 978-1-4244-9472-9 | 978-1-4244-9472-9 | 4 |
PageRank | References | Authors |
0.57 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Barry M. Trager | 1 | 614 | 97.81 |
| Chai Wah Wu | 2 | 330 | 67.62 |
| Mikel Stanich | 3 | 13 | 1.85 |
| Kartheek Chandu | 4 | 16 | 2.77 |