Name
Abstract | ||
|---|---|---|
An efficient technique for early detection of undecodable blocks during LDPC decoding is introduced. The proposed method avoids unnecessary decoding iterations by predicting decoding failure and therefore results in significant improvement in power and latency in low SNR values. The proposed method which has a low hardware overhead compares the parity checksum against predefined threshold values for three iterations and terminates decoding if a condition is met. A 5.25 mm2 10GBASE-T Split-Row Threshold decoder is implemented using the proposed technique in 65 nm CMOS. The postlayout results show that at low SNR value of 3.0 dB, the decoder requires 2.3 times fewer decoding iterations which results in 23 pJ/bit energy dissipation. This is 2.4 times lower than the energy dissipation of Split-Row Threshold decoder without the proposed early stopping technique. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISCAS.2011.5937929 | Circuits and Systems |
Keywords | Field | DocType |
CMOS logic circuits,block codes,decoding,iterative methods,low-power electronics,parity check codes,100BASE-T split row threshold decoder,LDPC decoding,decoding failure prediction,early detection,early stopping technique,energy dissipation,low SNR value,low power LDPC decoder,predefined threshold value,undecodable block,unnecessary decoding iteration,10GBASE-T,65 nm CMOS,LDPC,early termination,energy efficiency,full parallel,low power,undecodable blocks | Early stopping,Checksum,Computer science,Low-density parity-check code,Block code,Electronic engineering,Soft-decision decoder,Decoding methods,Bit error rate,Low-power electronics | Conference |
ISSN | ISBN | Citations |
0271-4302 E-ISBN : 978-1-4244-9472-9 | 978-1-4244-9472-9 | 7 |
PageRank | References | Authors |
0.66 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tinoosh Mohsenin | 1 | 406 | 47.43 |
| Houshmand Shirani-mehr | 2 | 7 | 0.66 |
| Bevan M. Baas | 3 | 295 | 27.78 |