Title
A scalable massively parallel processor for real-time image processing
Abstract
A processor with 2048 4 b grained processor elements (PE) and a 2 Mb SRAM is implemented in 65 nm CMOS and occupies a 5.29 mm2 die. It achieves 200 MHz operation at 1.0 V and outputs peak power efficiency of 310 GOPS/W. The peak performance reached 191 GOPS at 560 MHz and 1.2 V in the double frequency mode. The processor can be optimized for both power and area by changing the number of PEs from 256 to 2048.
Year
DOI
Venue
2010
10.1109/ISSCC.2010.5433910
Solid-State Circuits Conference Digest of Technical Papers
Keywords
DocType
Volume
parallel processing,cmos integrated circuits,high area efficiency,simd,fine grained processing element,image processing,power efficiency,area efficiency,processing elements,frequency 200 mhz,grained processor elements,scalable massively parallel single-instruction multiple-data processor,higher power efficiency,multimedia system-on-a-chip,image processor,simd processor,scalable massively parallel processor,system-on-chip,digital signal processing chips,normal frequency mode,soc,electronic devices,peak power efficiency,sram,controller overhead cycles,scalable architecture,double frequency mode,real-time image processing,cmos,multimedia communication,simd parallel processing unit,real-time systems,real-time image processing technology,voltage 1.0 v,higher performance,system on a chip,real time systems,registers,layout,pipelines,silicon,media,computer architecture
Conference
46
Issue
ISSN
ISBN
10
0193-6530
978-1-4244-6033-5
Citations 
PageRank 
References 
5
0.60
4
Authors
13