Paper Info
Title
An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads
Abstract
This paper addresses performance issues encountered in parallel functional gate-level simulation executed on multi-core machine. It demonstrates that a straightforward application of the multi-core simulation on a multi-core machine does not improve simulation performance. This is due to unbalanced partitioning, lack of sufficient concurrency in the design partitions, overhead due to communication between partitions, and synchronization overhead imposed by the simulator. We propose, implement and automate a generic (partitioning-independent) prediction-based solution to eliminate or minimize communication and synchronization overhead in an event-driven functional gate-level simulation on a multi-core machine. We demonstrate speedup obtained with this method on a set of real Opensource designs.
Year
DOI
Venue
2013
10.1109/MTV.2013.20
Microprocessor Test and Verification
Keywords
Field
DocType
circuit simulation,logic design,logic gates,multiprocessing systems,synchronisation,Opensource designs,communication overhead minimization,design partitions,event-driven functional gate-level simulation,generic prediction-based solution,multicore functional gate-level simulation,multicore machine,parallel functional gate-level simulation,partitioning-independent prediction-based solution,synchronization overhead minimization,Gate-level simulation,RTL,multi-core simulation,multicore computing,parallel simulation,single-core simulation,synchronization and communication overheads
Computer architecture,Parallel simulation,Synchronization,Concurrency,Computer science,Multicore computing,Real-time computing,Logic simulation,Multi-core processor,Speedup,Overhead (business),Embedded system
Conference
ISSN
Citations 
PageRank 
1550-4093
1
0.48
References 
Authors
5
2
Name
Order
Citations
PageRank
Tariq Bashir Ahmad110.48
Maciej J. Ciesielski262974.80