Paper Info
Title
A DRAM Centric NoC Architecture and Topology Design Approach
Abstract
Most communication traffic in today's System on Chips (SoC) is DRAM centric. The NoC should be designed to efficiently handle the many-to-one communication pattern, funneling to and from the DRAM controller. In this paper, we motivate the use of a separate network for the DRAM traffic and justify the power overhead and performance improvement obtained, when compared to traditional solutions. We also show how the topology of this DRAM network can be designed and optimized to account for the funnel-shaped pattern. Our experiments on a realistic SoC multimedia benchmark shows a large reduction in power consumption and improvement in performance when compared to existing solutions.
Year
DOI
Venue
2011
10.1109/ISVLSI.2011.60
ISVLSI
Keywords
Field
DocType
DRAM chips,network topology,network-on-chip,system-on-chip,DRAM centric NoC architecture,DRAM controller,DRAM traffic,SoC multimedia benchmark,funnel-shaped pattern,power consumption,system on chips,topology design approach,DRAM,Network-on-Chip (NoC)
Dram,Architecture,Control theory,System on a chip,Network on a chip,Network topology,Engineering,CAS latency,Performance improvement,Embedded system
Conference
ISSN
ISBN
Citations 
2159-3469 E-ISBN : 978-0-7695-4447-2
978-0-7695-4447-2
3
PageRank 
References 
Authors
0.38
17
4
Name
Order
Citations
PageRank
Ciprian Seiculescu12199.26
Srinivasan Murali2215596.64
Luca Benini3131161188.49
Giovanni De Micheli4102451018.13