Paper Info
Title
A 0.5 V Operation Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems
Abstract
A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. To realize the low power LSIs it is important to decrease the supply voltage (VDD) to e.g., 0.5 V because the active power consumption of LSIs strongly depends on VDD. When the 0.5 V VDD is adopted, widely used RAM, SRAM is difficult to operate because the SRAM is sensitive to the VTH variation. DRAM has a potential to operate at such low VDD. As the key technology to realize 0.5 V operation DRAM, this paper proposes the word-line booster circuit. The theoretical equation of the output voltage and the energy consumption of the proposed booster is extensively investigated. The proposed booster outputs 1.4 V in 3 clock cycles, which is shorter than the DRAM access time and the power consumption is 60 pJ. 1.4 V is the required word-line voltage to successfully charge the DRAM cell capacitor. Compared with the conventional boosters, the rising time and the power consumption are decreased to 38% and 68%, respectively, with the same circuit area. The proposed circuit was fabricated with the 0.18 μm standard CMOS process and the high-speed boosting is experimentally demonstrated.
Year
DOI
Venue
2011
10.1109/JSSC.2011.2163355
Solid-State Circuits, IEEE Journal of
Keywords
DocType
Volume
CMOS logic circuits,DRAM chips,SRAM chips,VLSI,low-power electronics,DRAM word-line booster circuit,SRAM,high-speed boosting,size 0.18 mum,standard CMOS process,ultra low power VLSI systems,voltage 0.5 V,voltage 1.4 V,Charge pump,DRAM,SRAM,low power,word-line booster
Journal
46
Issue
ISSN
Citations 
10
0018-9200
0
PageRank 
References 
Authors
0.34
0
2
Name
Order
Citations
PageRank
Shuhei Tanakamaru112118.35
Ken Takeuchi28843.27