Name
Abstract | ||
|---|---|---|
The paper introduces a novel test data compression scheme, which is primarily devised for low power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide ATPG to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TCAD.2015.2432133 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | Field | DocType |
design for testability,embedded deterministic test,low power test,scan-based designs,test compression | Residual,Automatic test pattern generation,Logic gate,System on a chip,Computer science,Real-time computing,Electronic engineering,Compression ratio,Test compression,Encoding (memory),Cube | Journal |
Volume | Issue | ISSN |
PP | 99 | 0278-0070 |
Citations | PageRank | References |
4 | 0.42 | 0 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Amit Kumar 0004 | 1 | 4 | 0.42 |
| M. Kassab | 2 | 326 | 10.84 |
| Elham Moghaddam | 3 | 79 | 7.05 |
| Nilanjan Mukherjee | 4 | 801 | 57.26 |
| Janusz Rajski | 5 | 2460 | 201.28 |
| Sudhakar M. Reddy | 6 | 5747 | 699.51 |
| Jerzy Tyszer | 7 | 838 | 74.98 |
| Chen Wang | 8 | 253 | 15.83 |