Name
Abstract | ||
|---|---|---|
This paper reviews the theory and introduces the architecture for a clock source with low phase noise and for measuring timing jitter. This approach utilizes a sample mean and sum of two random variables, and can be implemented in CMOS or SiGe BiCMOS circuits. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ATS.2012.15 | Asian Test Symposium |
Keywords | Field | DocType |
BiCMOS digital integrated circuits,clocks,timing jitter,BiCMOS circuit,clock source,low phase noise,post silicon jitter measurement,timing jitter measurement,bias error,cumulative distribution function,fail counter,histogram,probability density function,random error,random variable | Phase-locked loop,Random variable,Computer science,Phase noise,Real-time computing,Electronic engineering,CMOS,Cumulative distribution function,Jitter,Probability density function,Phase frequency detector | Conference |
ISSN | ISBN | Citations |
1081-7735 E-ISBN : 978-0-7695-4876-0 | 978-0-7695-4876-0 | 0 |
PageRank | References | Authors |
0.34 | 8 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kiichi Niitsu | 1 | 0 | 0.34 |
| Takahiro J. Yamaguchi | 2 | 5 | 2.32 |
| Masahiro Ishida | 3 | 105 | 22.58 |
| Haruo Kobayashi | 4 | 27 | 7.46 |