Name
Abstract | ||
|---|---|---|
A 567 mm2 processor on 45 nm CMOS integrates 48 IA-32 cores and 4 DDR3 channels in a 6Ã4 2D-mesh network. Cores communicate through message passing using 384 KB of on-die shared memory. Fine-grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. As performance scales, the processor dissipates between 25 W and 125 W. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ISSCC.2010.5434077 | Solid-State Circuits Conference Digest of Technical Papers |
Keywords | Field | DocType |
message passing,microprocessor chips,power aware computing,shared memory systems,2D mesh network,48-core IA-32 message-passing processor,CMOS,DVFS,fine-grain power management,message passing,on-die shared memory,size 45 nm | Memory bandwidth,Shared memory,CPU cache,Computer science,CMOS,Chip,Bandwidth (signal processing),Frequency scaling,Computer hardware,Message passing,Embedded system | Conference |
ISSN | ISBN | Citations |
0193-6530 | 978-1-4244-6033-5 | 312 |
PageRank | References | Authors |
13.00 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Howard, J. | 1 | 312 | 13.00 |
| Dighe, S. | 2 | 840 | 32.79 |
| Hoskote, Y. | 3 | 312 | 13.00 |
| Sriram R. Vangal | 4 | 1857 | 114.54 |