Name
Abstract | ||
|---|---|---|
An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of 126.5 dBc/Hz at 20.1 GHz and 124.2 dBc/Hz at 24 GHz |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/JSSC.2013.2239114 | Solid-State Circuits, IEEE Journal of |
Keywords | Field | DocType |
Bandwidth calibration,PLL,frequency synthesizers,phase locked loop | Dual loop,Phase-locked loop,Capacitor,Control theory,Computer science,Phase noise,Electronic engineering,CMOS,Voltage-controlled oscillator,Transfer function,dBc | Journal |
Volume | Issue | ISSN |
48 | 4 | 0018-9200 |
Citations | PageRank | References |
12 | 1.29 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ferriss, M. | 1 | 12 | 1.29 |
| Plouchart, J.-O. | 2 | 31 | 5.54 |
| Natarajan, A. | 3 | 14 | 1.69 |
| Rylyakov, A. | 4 | 19 | 6.68 |