Name
Title | ||
|---|---|---|
A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator |
Abstract | ||
|---|---|---|
A fully on-chip CMOS relaxation oscillator (ROSC) with a PVT variation compensation circuit is proposed in this paper. The circuit is based on a conventional ROSC and has a distinctive feature in the compensation circuit that compensates for comparator's non-idealities caused by offset voltage and delay time. We also developed a bias circuit consisting of positive and negative temperature coefficient resistors to obtain the temperature compensated clock frequency. Measurement results demonstrated that the circuit can generate a stable clock frequency of 6.66 kHz. The power dissipation was 940 nW. The measured line regulation and temperature coefficient were 0.98%/V and 56ppm/°C, respectively. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ICECS.2012.6463790 | Electronics, Circuits and Systems |
Keywords | Field | DocType |
CMOS integrated circuits,comparators (circuits),relaxation oscillators,resistors,PVT variation compensation circuit,bias circuit,comparator,delay time,frequency 6.66 kHz,negative temperature coefficient resistors,offset voltage,on-chip CMOS relaxation oscillator,positive temperature coefficient resistors,power 940 nW | Discrete circuit,Relaxation oscillator,Comparator,Input offset voltage,Computer science,Line regulation,CMOS,Electronic engineering,Resistor,Electrical engineering,Clock rate | Conference |
ISBN | Citations | PageRank |
978-1-4673-1259-2 | 3 | 0.55 |
References | Authors | |
4 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keishi Tsubaki | 1 | 3 | 0.55 |
| Tetsuya Hirose | 2 | 3 | 0.55 |
| Yuji Osaki | 3 | 40 | 5.48 |
| Seiichiro Shiga | 4 | 4 | 0.95 |
| Nobutaka Kuroki | 5 | 3 | 0.55 |
| Masahiro Numa | 6 | 82 | 20.87 |