Name
Title | ||
|---|---|---|
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating |
Abstract | ||
|---|---|---|
Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming the serious power-consumption problem that has rapidly become a dominant constraint on the performance improvement of today's VLSI processors. Normally-off and instant-on capabilities with a small area penalty due to non-volatility and three-dimensional-stackability of MTJ devices in the above structure allow us to apply a power-gating technique in a fine temporal granularity, which can perfectly eliminate wasted power dissipation due to leakage current. The impact of embedding nonvolatile memory devices into a logic circuit was, however, demonstrated by using only small fabricated primitive logic-circuit elements [3], memory-like structures such as FPGA [4], or circuit simulation because of the lack of an established MTJ-oriented design flow reflecting the chip-fabrication environment, while larger-capacity and/or high-speed-access MRAM has been increasingly developed. In this paper, we present an MTJ/MOS-hybrid video coding hardware that uses a cycle-based power-gating technique for a practical-scale MTJ-based NV-LIM LSI, which is fully designed using the established semi-automated MTJ-oriented design flow. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISSCC.2013.6487696 | Solid-State Circuits Conference Digest of Technical Papers |
Keywords | DocType | Volume |
CMOS logic circuits,MRAM devices,VLSI,field programmable gate arrays,magnetic tunnelling,video coding,CMOS logic-circuit plane,FPGA,MTJ-MOS devices,MTJ-MOS-hybrid video coding hardware,NV-LIM architecture,VLSI processors,chip-fabrication environment,circuit simulation,cycle-based power-gating technique,high-speed-access MRAM,leakage current,leakage reduction,magnetic tunnel junction devices,memory-like structures,nonvolatile logic-in-memory array processor,nonvolatile memory devices,power-consumption problem,practical-scale MTJ-based NV-LIM LSI,primitive logic-circuit elements,semiautomated MTJ-oriented design flow,size 90 nm,three-dimensional-stackability,wasted power dissipation elimination | Conference | 56 |
ISSN | ISBN | Citations |
0193-6530 | 978-1-4673-4515-6 | 18 |
PageRank | References | Authors |
1.26 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masanori Natsui | 1 | 80 | 15.10 |
| Suzuki, D. | 2 | 18 | 1.26 |
| Sakimura, N. | 3 | 18 | 1.26 |
| Nebashi, R. | 4 | 18 | 1.26 |