Paper Info
Title
Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications
Abstract
Unified solid-state storage (USSS) provides high error tolerance with four techniques: reverse-mirroring (RM), error-reduction synthesis (ERS), page-RAID, and error-masking (EM). The acceptable raw bit-error rate (ABER) of NAND flash memory is enhanced by 32×, or endurance or data-retention time effectively extends by 4.2 or 34×, respectively. ABER is defined to realize BER after ECC below 10-15.
Year
DOI
Venue
2013
10.1109/ISSCC.2013.6487711
Solid-State Circuits Conference Digest of Technical Papers
Keywords
Field
DocType
NAND circuits,error statistics,flash memories,ABER,ECC,EM,ERS,NAND flash memory,RM,ReRAM,USSS,acceptable raw bit-error rate,big-data applications,data-retention time,endurance time,error tolerance,error-masking,error-reduction synthesis,page-RAID,reverse-mirroring,unified solid-state-storage architecture
Nand flash memory,Architecture,Flash file system,Error tolerance,Computer science,Computer hardware,Solid-state storage,Big data,Resistive random-access memory
Conference
Volume
ISSN
ISBN
56
0193-6530
978-1-4673-4515-6
Citations 
PageRank 
References 
5
1.28
3
Authors
3
Name
Order
Citations
PageRank
Shuhei Tanakamaru112118.35
Masafumi Doi2172.69
Takeuchi, K.3283.09