Paper Info
Title
Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme
Abstract
11-times extended lifetime, 76% reduced error SSD is proposed. The error-prediction LDPC realizes both 7-times faster read and high reliability. Errors are most efficiently corrected by calibrating memory data based on the VTH, inter-cell coupling, write/erase cycles and data-retention time. The error-recovery scheme with a program-disturb error-recovery pulse and a data-retention error-recovery pulse is also proposed to reduce the program-disturb error and the data-retention error by 76% and 56%, respectively.
Year
DOI
Venue
2013
10.1109/ASPDAC.2013.6509567
Design Automation Conference
Keywords
Field
DocType
NAND circuits,error correction codes,flash memories,parity check codes,reliability,EP-LDPC,SSD,data-retention error-recovery pulse,error prediction LDPC,intercell coupling,low density parity check codes,memory data calibration,program-disturb error-recovery pulse,solid-state drives,write-erase cycles
Forward error correction,Architecture,Coupling,Computer science,Low-density parity-check code,Turbo code,Real-time computing,Pulse (signal processing),Electronic engineering,Solid-state,Calibration
Conference
ISSN
ISBN
Citations 
2153-6961
978-1-4673-3029-9
2
PageRank 
References 
Authors
0.43
2
3
Name
Order
Citations
PageRank
Shuhei Tanakamaru112118.35
Yuki Yanagihara2474.70
Takeuchi, K.3283.09