Title
Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation
Abstract
Linear Feedback Shift Registers (LFSRs) have been extensively used for compressed manufacturing test. They have been recently employed as a foundation for porting constrained-random stimuli from a pre-silicon verification environment to in-system validation. This work advances this concept by improving both the hardware efficiency and the duration of in-system validation experiments.
Year
DOI
Venue
2013
10.1145/2463209.2488882
Design Automation Conference
Keywords
Field
DocType
formal verification,logic testing,shift registers,LFSR,constrained-random stimuli,hardware-efficient on-chip generation,in-system validation,linear feedback shift register,presilicon verification environment,time-extensive constrained-random sequences,Constrained-Random Sequences,In-System Validation
System validation,Shift register,Post-silicon validation,Computer science,Logic testing,Electronic engineering,Real-time computing,Porting,Computer hardware,Formal verification
Conference
ISSN
Citations 
PageRank 
0738-100X
4
0.42
References 
Authors
13
3
Name
Order
Citations
PageRank
Adam B. Kinsman114110.05
Ho Fai Ko223414.44
Nicola Nicolici380759.91