Name
Abstract | ||
|---|---|---|
Radiation-induced Multiple Event Transients (METs) are expected to become more frequent than Single Event Transients (SETs) at nanoscale CMOS technology nodes. In this paper, a fast and accurate layout-based Soft Error Rate (SER) assessment technique with consideration of both SET and MET fault models is presented. Despite existing techniques in which the adjacent MET sites are extracted from a logic-level netlist, we conduct a comprehensive layout analysis to obtain MET adjacent cells. Experimental results reveal that the layout-based technique is the only viable solution for identification of the adjacent cells as netlist-based techniques considerably underestimate the overall SER. Furthermore, by identifying the most vulnerable adjacent cells and increasing their physical distance in the layout using local adjustment rules, we are able to considerably reduce the overall SER without imposing any area and performance penalty. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TCAD.2015.2459053 | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions |
Keywords | Field | DocType |
Multiple Bit Upset,Multiple Event Transient,Reliability,Soft Errors | Netlist,Logic gate,Soft error,Computer science,Nanoscale cmos,Real-time computing,Electronic engineering,Comprehensive layout,Transient analysis,Benchmark (computing) | Journal |
Volume | Issue | ISSN |
PP | 99 | 0278-0070 |
Citations | PageRank | References |
7 | 0.71 | 20 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mojtaba Ebrahimi | 1 | 336 | 24.74 |
| Hossein Asadi | 2 | 323 | 31.94 |
| Rajendra Bishnoi | 3 | 132 | 19.64 |
| Mehdi B. Tahoori | 4 | 1537 | 163.44 |