| Mitigating Read Failures in STT-MRAM | 0 | 0.34 | 2020 |
| Crossover-Aware Placement And Routing For Inkjet Printed Circuits | 0 | 0.34 | 2020 |
| Approximate Spintronic Memories | 0 | 0.34 | 2020 |
| Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects | 0 | 0.34 | 2020 |
| A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology | 2 | 0.46 | 2020 |
| Secure STT-MRAM Bit-Cell Design Resilient to Differential Power Analysis Attacks | 0 | 0.34 | 2020 |
| A Universal Spintronic Technology based on Multifunctional Standardized Stack | 1 | 0.37 | 2020 |
| A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit. | 0 | 0.34 | 2020 |
| Predictive Modeling and Design Automation of Inorganic Printed Electronics | 0 | 0.34 | 2019 |
| Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects | 0 | 0.34 | 2019 |
| A Spintronics Memory PUF for Resilience Against Cloning Counterfeit | 2 | 0.39 | 2019 |
| Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme | 1 | 0.36 | 2019 |
| A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach | 0 | 0.34 | 2019 |
| Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design | 0 | 0.34 | 2019 |
| A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM | 3 | 0.42 | 2019 |
| Variation-aware Fault Modeling and Test Generation for STT-MRAM | 0 | 0.34 | 2019 |
| Inkjet-Printed True Random Number Generator Based On Additive Resistor Tuning | 0 | 0.34 | 2019 |
| Reliable in-memory neuromorphic computing using spintronics. | 2 | 0.39 | 2019 |
| Multi-Bit Non-Volatile Spintronic Flip-Flop | 0 | 0.34 | 2018 |
| Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications | 1 | 0.37 | 2018 |
| VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool. | 1 | 0.35 | 2018 |
| Using Multifunctional Standardized Stack As Universal Spintronic Technology For Iot | 1 | 0.35 | 2018 |
| Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM | 5 | 0.45 | 2018 |
| Spintronic normally-off heterogeneous system-on-chip design | 0 | 0.34 | 2018 |
| Inkjet-Printed EGFET-Based Physical Unclonable Function - Design, Evaluation, and Fabrication. | 2 | 0.51 | 2018 |
| A Cross-Layer Adaptive Approach For Performance And Power Optimization In Stt-Mram | 2 | 0.36 | 2018 |
| Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM. | 0 | 0.34 | 2018 |
| Parametric failure modeling and yield analysis for STT-MRAM | 0 | 0.34 | 2018 |
| Architecting SOT-RAM Based GPU Register File | 0 | 0.34 | 2017 |
| Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops. | 3 | 0.41 | 2017 |
| Opportunistic write for fast and reliable STT-MRAM. | 0 | 0.34 | 2017 |
| VAET-STT: A variation aware estimator tool for STT-MRAM based memories. | 2 | 0.46 | 2017 |
| GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack | 1 | 0.40 | 2017 |
| A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing | 4 | 0.41 | 2016 |
| Layout-based Modeling and Mitigation of Multiple Event Transients | 7 | 0.71 | 2016 |
| Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices. | 1 | 0.35 | 2016 |
| Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing | 2 | 0.39 | 2016 |
| Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches. | 0 | 0.34 | 2016 |
| Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing. | 11 | 1.06 | 2016 |
| Fault Tolerant Non-Volatile spintronic flip-flop | 1 | 0.36 | 2016 |
| Self-Timed Read and Write Operations in STT-MRAM. | 3 | 0.40 | 2016 |
| Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy | 29 | 1.24 | 2015 |
| Read disturb fault detection in STT-MRAM | 18 | 0.92 | 2014 |
| Avoiding unnecessary write operations in STT-MRAM for low power implementation | 17 | 0.70 | 2014 |
| Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM | 10 | 0.63 | 2014 |
