Paper Info
Title
Deadspace-aware Power/Ground TSV planning in 3D floorplanning
Abstract
The reliable Power Delivery Network (PDN) design is a challenging aspect in Three-Dimensional-Integrated-Circuits (3D-ICs). In order to ensure the robustness of the 3D PDN, the number and the locations of the Power/Ground (P/G) Through-Silicon-Vias (TSVs) should be carefully planned. Non-regular P/G TSV placement has superior performance compared to the regular one in terms of TSV count. However, the corresponding deadspace optimization is necessary, which complicates the traditional 3D floorplanning. In this work, we propose an efficient deadspace-aware P/G TSV planning combined with the 3D floorplanning to simultaneously place the 2D blocks and P/G TSVs to minimize the total wirelength and the number of inserted TSVs under IR-drop and fixed-outline constraints.
Year
DOI
Venue
2015
10.1109/ICICDT.2015.7165894
ICICDT
Keywords
Field
DocType
benchmark testing,optimization,planning,estimation,measurement
Electronic engineering,Robustness (computer science),Engineering,Benchmark (computing),Floorplan,Embedded system
Conference
Citations 
PageRank 
References 
0
0.34
8
Authors
4
Name
Order
Citations
PageRank
Shengcheng Wang1134.29
Farshad Firouzi227520.28
Fabian Oboril328826.71
Mehdi B. Tahoori41537163.44