Paper Info
Title
Hardware implementation of the Totally Self-Checking SHA-256 hash core
Abstract
Hashing cores are utilized by many existing high performance cryptographic systems, used in security schemes such as SET, PKI, and IPSec. Efficient operation of these hardware modules can be degraded, especially when they operate in harsh environments i.e. space applications, military or medical applications. In this paper, a Totally Self-Checking (TSC) design is introduced for the SHA-256 hash function, suitable for harsh environments. The achieved fault coverage is 100% in the case of odd erroneous bits. The same coverage is achieved for even number of erroneous bits, if they are appropriately propagated. Performance measurements are reported for ASIC and reconfigurable technologies, highlighting issues that must be respected by the designer. The introduced TSC hashing core is area-efficient by 19%, compared to the corresponding Duplicated with Checking (DWC) one.
Year
DOI
Venue
2015
10.1109/EUROCON.2015.7313715
EUROCON 2015 - International Conference Computer as a Tool
Keywords
Field
DocType
application specific integrated circuits,cryptography,file organisation,ASIC technologies,DWC,IPSec,PKI,SET,TSC design,cryptographic systems,duplicated with checking,hardware modules,harsh environments,medical applications,military applications,odd erroneous bits,performance measurements,reconfigurable technologies,security schemes,space applications,totally self-checking SHA-256 hash core,Concurrent Error Detection,Cryptography,Hash Functions,Safety,Security,Totally Self-Checking Circuit
SHA-2,Computer science,Universal hashing,Hash function,Computer hardware,Security of cryptographic hash functions,2-choice hashing,Hash chain,Dynamic perfect hashing,Hash table
Conference
ISBN
Citations 
PageRank 
978-1-4799-8568-5
2
0.38
References 
Authors
6
4
Name
Order
Citations
PageRank
harris e michail115618.29
Kotsiolis, A.220.38
A. P. Kakarountas3605.71
Athanasiou, G.420.38