Paper Info
Title
A High-Speed Analog Min-Sum Iterative Decoder
Abstract
Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. Proposed circuits are devised based on current mirrors. Therefore, in any fabrication technology that accurate current mirrors can be designed, analog NIS decoders can be implemented. The functionality of the proposed modules was verified by implementing an analog MS decoder for a (32,8,10) regular LDPC code in 0.18-mu m CMOS technology. In low signal to noise ratios when the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steady-state condition surpasses that of the conventional NIS decoder, and is close to the performance predicted by the earlier work on the dynamics of the continuous-time analog decoding by Hemati and Banihashemi, ISIT2004. At a throughput of 24Mb/s, loss in the coding gain compared to the conventional NIS decoder at BER of 10(-3) is about 0.3dB. To the best of our knowledge, this decoder has the highest throughput and the lowest power/speed ratio among the reported analog CMOS iterative decoders.
Year
DOI
Venue
2005
10.1109/ISIT.2005.1523649
2005 IEEE INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY (ISIT), VOLS 1 AND 2
Keywords
Field
DocType
cmos technology,coding gain,measurement error,steady state,signal to noise ratio,ldpc code,chip,current mirrors
Discrete mathematics,Coding gain,Computer science,Low-density parity-check code,Signal-to-noise ratio,Real-time computing,CMOS,Electronic engineering,Chip,Soft-decision decoder,Decoding methods,Electronic circuit
Conference
Citations 
PageRank 
References 
0
0.34
6
Authors
3
Name
Order
Citations
PageRank
Saied Hemati111913.64
Amir H. Banihashemi249054.61
Calvin Plett313420.84