Title
A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond
Year
Venue
Keywords
2004
CICC
system on chip,error correction,logic design,integrated circuit design,soft error
Field
DocType
Citations 
Logic gate,System on a chip,Soft error,Computer science,Electronic engineering,CMOS,Error detection and correction,Integrated circuit design,Electronic circuit,Asynchronous circuit
Conference
9
PageRank 
References 
Authors
1.04
0
5
Name
Order
Citations
PageRank
Yoshihide Komatsu1265.22
Yukio Arima2162.81
tetsuya fujimoto391.04
Takahiro Yamashita4182.86
Koichiro Ishibashi5348.76