A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications - Citegraph

Paper Info

Title
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications

Abstract
The paper presents the design of a 2.488 - 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. The transceiver makes use of a low-jitter LC PLL to enable high-reliability system design. A system modeling approach is also described, which is used for optimizing the architectural trade-offs. The design has 520fs RJ(rms) and consumes 30.1 mW/Gbps at 11.2 Gbps.

Year	DOI	Venue
2012	10.1109/MWSCAS.2012.6291943	Midwest Symposium on Circuits and Systems Conference Proceedings
Keywords	Field	DocType
transmitters,phase locked loops,cmos integrated circuits,field programmable gate arrays,transceivers,jitter	Phase-locked loop,Transceiver,Computer science,Field-programmable gate array,Systems design,CMOS,Electronic engineering,Systems modeling,Jitter,SerDes,Embedded system	Conference
ISSN	Citations	PageRank
1548-3746	2	0.51
References	Authors
4	17

Authors (17 rows)

Cited by (2 rows)

References (4 rows)

Name	Order	Citations	PageRank
Socrates D. Vamvakos	1	14	3.62
Claude R. Gauthier	2	5	2.23
Chethan Rao	3	3	0.93
karthisha ramoshan canagasaby	4	2	0.51
prashant choudhary	5	5	1.93
s dabral	6	2	0.51
Shaishav Desai	7	11	3.75
Mahmudul Hassan	8	53	9.98
k c hsieh	9	2	0.51
Bendik Kleveland	10	26	3.91
Gurupada Mandal	11	3	0.93
Richard Rouse	12	8	2.39
Ritesh Saraf	13	3	0.93
Alvin Wang	14	3	0.93
Jason Yeung	15	3	1.27
Khaldoon Abugharbieh	16	14	6.37
Ying Cao	17	57	9.01

1