Title
A Survey of Architectural Techniques for Near-Threshold Computing
Abstract
Energy efficiency has now become the primary obstacle in scaling the performance of all classes of computing systems. Low-voltage computing, specifically, near-threshold voltage computing (NTC), which involves operating the transistor very close to and yet above its threshold voltage, holds the promise of providing many-fold improvement in energy efficiency. However, use of NTC also presents several challenges such as increased parametric variation, failure rate, and performance loss. This article surveys several recent techniques that aim to offset these challenges for fully leveraging the potential of NTC. By classifying these techniques along several dimensions, we also highlight their similarities and differences. It is hoped that this article will provide insights into state-of-the-art NTC techniques to researchers and system designers and inspire further research in this field.
Year
DOI
Venue
2016
10.1145/2821510
JETC
Keywords
Field
DocType
cache,classification,reliability,memory,low voltage
Obstacle,Cache,Computer science,Efficient energy use,Failure rate,Electronic engineering,Real-time computing,Parametric statistics,Low voltage,Threshold voltage,Offset (computer science)
Journal
Volume
Issue
ISSN
12
4
1550-4832
Citations 
PageRank 
References 
3
0.39
58
Authors
1
Name
Order
Citations
PageRank
Sparsh Mittal181750.36