Title
Efficient calibration scheme for high-resolution pipelined ADCs
Abstract
This paper describes a background calibration technique that linearizes pipelined ADCs by correcting for errors in the digital domain. This also relaxes the requirements for the analog components and enables power and area savings. The calibration technique doesn't require a separate reference ADC that samples the input, nor the generation of digital correlation signals or extra analog calibration components. The calibration technique is robust and easily implementable in any digital technology. The implementation of the digital calibration algorithm requires minimal digital resources and less than 1% of the overall ADC power consumption.
Year
DOI
Venue
2013
10.1109/MWSCAS.2013.6674735
Midwest Symposium on Circuits and Systems Conference Proceedings
Keywords
Field
DocType
calibration
Flight dynamics (spacecraft),Calibration algorithm,Computer science,Electronic engineering,Successive approximation ADC,Calibration,Digital resources,Power consumption
Conference
ISSN
Citations 
PageRank 
1548-3746
0
0.34
References 
Authors
8
2
Name
Order
Citations
PageRank
andreas larsson100.34
Jose Silva-Martinez263086.56