Jose Silva-Martinez

Author Info

Name	Affiliation	Papers
JOSE SILVA-MARTINEZ	Department of Electrical & Computer Eng., Texas A&M University, College Station, USA 77843-3128	93
Collaborators	Citations	PageRank
160	630	86.56
Referers	Referees	References
1484	1362	501

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Publications (93 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
An Interference-Tolerant Synchronization Scheme for Wireless Communication Systems Based on Direct Sequence Spread Spectrum	0	0.34	2022
Recent Advances on Linear Low-Dropout Regulators	0	0.34	2021
Thermoelectric Energy Harvesting for Implantable Medical Devices	0	0.34	2021
A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier	0	0.34	2020
A 3 to 6 GHz Highly Linear I-Channel Receiver with over +3.0 dBm In-Band P1dB and 200 MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications	0	0.34	2020
A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator	3	0.38	2020
MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems	0	0.34	2020
An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method	0	0.34	2020
A Low-cost On-chip Built-in Self-test Solution for ADC Linearity Test	0	0.34	2020
A Blind Calibration Scheme for Switched-Capacitor Pipeline Analog-to-Digital Converters	0	0.34	2020
An Efficient Sinusoid-Like Pseudo Random Sequence Modulator/Demodulator System With Reduced Adjacent Channel Leakage and High Rejection to Random and Systematic Interference	0	0.34	2020
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration	0	0.34	2019
A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers	0	0.34	2019
A 3-6-GHz Highly Linear I-Channel Receiver With Over +3.0-dBm In-Band P1dB and 200-MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications	1	0.39	2019
Efficient Broadband Class AB Amplifier	0	0.34	2019
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.	2	0.45	2018
Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits.	0	0.34	2018
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs.	1	0.40	2018
Low noise RF quadrature VCO using tail-switch network-based coupling in 40 nm CMOS	0	0.34	2018
A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications.	0	0.34	2018
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS.	0	0.34	2017
A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques.	3	0.48	2017
Low-Power Gm-C Filter Employing Current-Reuse Differential Difference Amplifiers.	0	0.34	2017
Low-Power ${G}_{{m}}{-}C$ Filter Employing Current-Reuse Differential Difference Amplifiers	2	0.41	2017
Algorithmic-pipelined ADC with a modified residue curve for better linearity	0	0.34	2017
High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications	0	0.34	2017
Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices.	1	0.35	2017
A 200MSPS time-interleaved 12-bit ADC system with digital calibration	0	0.34	2017
A 13bit 200ms/S Pipeline Adc With Current-Mode Mdacs	0	0.34	2017
A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage.	1	0.37	2017
Multitone ACLR and Its Applications to Linear PA Design.	0	0.34	2017
A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration	1	0.37	2016
A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer.	0	0.34	2016
A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS.	3	0.57	2016
Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma–Delta Modulators	3	0.41	2015
A 75 MHz BW 68dB DR CT-Sigma Delta Modulator with Single Amplifier Biquad Filter and A Broadband Low-power Common-gate Summing Technique	1	0.43	2015
A 0.6ps Jitter 2-16 Ghz 130nm Cmos Frequency Synthesizer For Broadband Applications	0	0.34	2015
General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators	2	0.41	2014
Design techniques for external capacitor-less LDOs with high PSR over wide frequency range	3	0.41	2014
Blocker tolerant wideband continuous time sigma-delta modulator for wireless applications	0	0.34	2014
Efficient calibration scheme for high-resolution pipelined ADCs	0	0.34	2013
Envelope tracking technique with bang-bang slew-rate enhancer for linear wideband RF PAs	0	0.34	2013
Robust compensation scheme for low power capacitor-less low dropout voltage regulator	1	0.35	2013
An external capacitor-less low drop-out regulator with superior PSR and fast transient response	3	0.49	2013
Blocker and jitter tolerant wideband ΣΔ modulators	0	0.34	2012
UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations	6	0.61	2012
Low-power 3 rd -order continuous-time low-pass sigma-delta analog-to-digital converter for wideband applications	1	0.40	2012
Corrections to “A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing” [Mar 11 507-520]	0	0.34	2011
Survey of Robustness Enhancement Techniques for Wireless Systems-on-a-Chip and Study of Temperature as Observable for Process Variations	3	0.47	2011
Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications	32	2.06	2010

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