Name
Abstract | ||
|---|---|---|
We present a deployment strategy for Error (slack-deficit) Detection Sequential (EDS) circuits to monitor non-critical paths of application systems at the clock falling edges, requiring neither buffer insertions nor extra clocks. The proposed strategy is applied to an FPGA-based Discrete Cosine Transform (DCT) unit together with EDS and Dynamic Voltage Scaling (DVS) circuits as a proof of concept. It is able to speculatively and accurately detect slack-deficits due to dynamic process, voltage and temperature (PVT) variations and correspondingly adjust the supply voltage. When processing realistic input data and operating at the same frequency as a highly-optimized baseline DCT implementation, our design produces equivalent outputs and incurs a 0.3% logic element overhead and 3.5% maximum frequency degradation, but saves up to 16.5% energy. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/MWSCAS.2015.7282186 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Keywords | Field | DocType |
radiation detectors,field programmable gate arrays | Dynamic voltage scaling,Particle detector,Computer science,Discrete cosine transform,Voltage,Field-programmable gate array,Electronic engineering,Proof of concept,Low voltage,Electronic circuit | Conference |
ISSN | Citations | PageRank |
1548-3746 | 0 | 0.34 |
References | Authors | |
6 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yaoqiang Li | 1 | 1 | 1.05 |
| Pierce I.-Jen Chuang | 2 | 1 | 1.38 |
| Andrew A. Kennings | 3 | 186 | 18.56 |
| Manoj Sachdev | 4 | 669 | 88.45 |