Name
Title | ||
|---|---|---|
An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASSCC.2011.6123637 | A-SSCC |
Keywords | Field | DocType |
amplifiers,high resolution,semiconductor devices,measurement system,system on a chip,integrated circuit design,duty cycle,chip | System on a chip,Computer science,Duty cycle,Electronic engineering,Real-time computing,CMOS,Clock skew,Static timing analysis,Integrated circuit design,Jitter,Amplifier | Conference |
Citations | PageRank | References |
2 | 0.41 | 6 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kiichi Niitsu | 1 | 126 | 38.14 |
| Masato Sakurai | 2 | 24 | 4.16 |
| Naohiro Harigai | 3 | 6 | 2.58 |
| Takahiro J. Yamaguchi | 4 | 34 | 4.61 |
| haruo kobayashi | 5 | 4 | 1.17 |