Name
Abstract | ||
|---|---|---|
With the advent of nanotechnology, transistors are getting smaller and growing in number according to Moore's Law. With this, the issue of heat dissipation is becoming of greater concern to researchers as the transistor heat dissipation reaches the Land Auer limit. Reversible logic is predicted to be an alternative to conventional computing due to lesser energy dissipation and exponentially faster problem-solving capacity. This paper introduces the design of a reversible ripple-carry adder using a mix of the well-known NCV library and the recently introduced NCV-|v1> library, with the assumption of a four-level quantum system. The results for the proposed adder are compared with previous ripple-carry adder designs. It then explores the design of a cost-optimized reversible ALU by modifying the above adder. Finally, a comparison of the proposed ALU is made with one of the latest reversible ALU designs. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISED.2014.56 | 2014 Fifth International Symposium on Electronic System Design |
Keywords | Field | DocType |
Reversible Logic,Quantum Gates,Adder,ALU | Quantum gate,Adder,Pass transistor logic,Dissipation,Arithmetic,Arithmetic logic unit,Electronic engineering,Serial binary adder,Carry-save adder,Three-input universal logic gate,Mathematics | Conference |
ISSN | Citations | PageRank |
2473-9421 | 1 | 0.38 |
References | Authors | |
3 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| subhankar pal | 1 | 32 | 5.27 |
| Chetan Vudadha | 2 | 11 | 5.77 |
| P. Sai Phaneendra | 3 | 15 | 4.84 |
| Sreehari Veeramachaneni | 4 | 43 | 10.65 |
| M. B. Srinivas | 5 | 28 | 11.05 |