Author Info
Name
Affiliation
Papers
SUBHANKAR PAL
Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science - Pilani, Hyderabad, India
14
Collaborators
Citations 
PageRank 
61
32
5.27
Referers 
Referees 
References 
142
219
52
Search Limit
100219
Title
Citations
PageRank
Year
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles00.342021
Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators00.342021
SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator10.352021
CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics00.342021
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm10.352021
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.20.372020
HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework00.342020
Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration40.412020
Sparse-TPU: adapting systolic arrays for sparse matrices50.482020
R2d3: A Reliability Engine For 3d Parallel Systems00.342020
Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective10.352019
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm00.342019
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator170.552018
A New Design of an N-Bit Reversible Arithmetic Logic Unit10.382014