Name
Abstract | ||
|---|---|---|
The recently proposed asynchronous nanowire crossbar architecture is envisioned to enhance the manufacturability and robustness of nanowire crossbar-based configurable digital circuits by removing various timing-related failure modes. Even though the proposed clock-free nanowire crossbar architecture has numerous technical merits over its clocked counterparts, it is still subject to high defect rates inherently induced by the nondeterministic nanoscale assembly of nanowire crossbars. To address this issue, a novel post-configuration repair strategy specific to the asynchronous nanowire crossbar architecture has been proposed. The proposed repair strategy is to selectively test highly defect-prone ON-state programmed crosspoints and reconfigure the given logic function to circumvent the ON-crosspoints tested as faulty by utilizing redundant rows/columns. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/MWSCAS.2012.6291985 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Keywords | Field | DocType |
Asynchronous nanowire crossbar architecture,Post-configuration repair,Defect & fault-tolerance,Functional testing,Redundancy | Asynchronous communication,Logic gate,Digital electronics,Computer science,Robustness (computer science),Electronic engineering,Fault tolerance,Design for manufacturability,Nanowire,Crossbar switch | Conference |
ISSN | Citations | PageRank |
1548-3746 | 0 | 0.34 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jun Wu | 1 | 20 | 2.57 |
| Yong-bin Kim | 2 | 338 | 55.72 |
| Minsu Choi | 3 | 156 | 27.63 |