Title
Secured-by-design FPGA: look-up tables and switch-boxes
Abstract
A circuit technique based on hardware replication improves the robustness of the FPGA circuitry against dynamic and/or static power attacks. Due to its nMOS-MUX based structure, the proposed circuit also exhibits an increased robustness against early evaluation attacks and those based on glitches. The secured LUT and switch are 3.4× and 1.5× larger than their standard counterparts, respectively. Given the achieved robustness against both dynamic and static power attacks, while FPGA configurability is preserved, this is a good trade-off.
Year
DOI
Venue
2015
10.1109/NORCHIP.2015.7364404
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
Keywords
Field
DocType
secured-by-design FPGA,look-up tables,LUT,switch-boxes,circuit technique,hardware replication,static power attacks,nMOS-MUX
Glitch,Lookup table,Computer science,Field-programmable gate array,Real-time computing,Robustness (computer science),Power demand,Transistor,Embedded system
Conference
Citations 
PageRank 
References 
1
0.35
20
Authors
2
Name
Order
Citations
PageRank
ziyad almohaimeed110.35
Mihai Sima29516.66