Name
Title | ||
|---|---|---|
Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process |
Abstract | ||
|---|---|---|
A novel, area-efficient transient power-rail electrostatic discharge (ESD) clamp circuit is proposed in this work. Current-mirror capacitors are used to reduce the layout area. Logic threshold voltages of inverters are modified to ensure a fully active on-state for the clamp device in ESD conditions. The proposed circuit reduces the layout area by about 56% compared with a circuit without current-mirror capacitors. Transmission line pulse (TLP) test results based on a 65-nm CMOS process demonstrate that the proposed circuit is an efficient on-chip ESD protection scheme for this process. In addition, the proposed circuit achieves a good immunity to mis-triggering with respect to fast power-up transitions. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1007/s11432-015-5398-3 | SCIENCE CHINA Information Sciences |
Keywords | DocType | Volume |
electrostatic discharge (ESD), power-rail clamp circuit, transmission line pulse (TLP), current mirror, mis-triggering, 静电放电, 电源钳位保护电路, 瞬态传输线脉冲, 电流镜, 误触发 | Journal | 59 |
Issue | ISSN | Citations |
4 | 1869-1919 | 1 |
PageRank | References | Authors |
0.40 | 4 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuan Wang | 1 | 17 | 13.39 |
| Guangyi Lu | 2 | 8 | 5.15 |
| haibing guo | 3 | 1 | 0.40 |
| Jian Cao | 4 | 7 | 4.76 |
| Song Jia | 5 | 6 | 7.00 |
| zhang | 6 | 10 | 9.77 |