| Robust Deep Learning Method to Detect Face Masks. | 0 | 0.34 | 2020 |
| Self-Heating Induced Variability And Reliability In Advanced Logic Devices And Circuits | 0 | 0.34 | 2019 |
| Deep insight into the voltage amplification effect from ferroelectric negative capacitance | 2 | 0.67 | 2019 |
| Improvement of thermal stability of nickel germanide using nitrogen plasma pretreatment for germanium-based technology. | 1 | 0.41 | 2018 |
| A 1-Gbps reference-less burst-mode CDR with embedded TDC in a 65-nm CMOS process. | 0 | 0.34 | 2018 |
| A Novel Tlp-Based Method To Deliver Iec 61000-4-2 Esd Stress | 0 | 0.34 | 2017 |
| Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process. | 0 | 0.34 | 2017 |
| Power-Rail Esd Clamp Circuit With Parasitic-Bjt And Channel Parallel Shunt Paths To Achieve Enhanced Robustness | 0 | 0.34 | 2017 |
| A 4.8-6.8 GHz low phase noise LC VCO in 0.13-µm CMOS technology. | 0 | 0.34 | 2016 |
| A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications | 1 | 0.43 | 2016 |
| Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics | 0 | 0.34 | 2016 |
| Distributed Voltage Security Monitoring in Large Power Systems Using Synchrophasors | 1 | 0.36 | 2016 |
| Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process. | 0 | 0.34 | 2016 |
| Optimization On Layout Strategy Of Gate-Grounded Nmos For On-Chip Esd Protection In A 65-Nm Cmos Process | 1 | 0.40 | 2016 |
| Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process | 1 | 0.40 | 2016 |
| A Low-Leakage Power Clamp Esd Protection Circuit With Prolonged Esd Discharge Time And Compact Detection Network | 0 | 0.34 | 2015 |
| Novel Dem Technique For Current-Steering Dac In 65-Nm Cmos Technology | 0 | 0.34 | 2015 |
| 180.5mbps-8gbps Dll-Based Clock And Data Recovery Circuit With Low Jitter Performance | 0 | 0.34 | 2015 |
| A Reference-Less All-Digital Burst-Mode Cdr With Embedded Tdc | 0 | 0.34 | 2015 |
| Four-Bit Transient-To-Digital Converter With A Single Rc-Based Detection Circuit For System-Level Esd Protection | 0 | 0.34 | 2015 |
| A 0.5–2 GHz high frequency selectivity RF front-end with series N-path filter | 1 | 0.36 | 2015 |
| Design On Multi-Bit Adder Using Sense Amplifier-Based Pass Transistor Logic For Near-Threshold Voltage Operation | 0 | 0.34 | 2015 |
| Cache Performance Optimization for SoC Vedio Applications. | 0 | 0.34 | 2014 |
| A UHF RFID reader transmitter with digital CMOS power amplifier | 0 | 0.34 | 2014 |
| Novel devices and process for 32 nm CMOS technology and beyond | 1 | 0.50 | 2008 |
| Novel devices and process for 32 nm CMOS technology and beyond | 1 | 0.50 | 2008 |
