Paper Info
Title
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm
Abstract
This paper presents an energy-efficient transmitter driver architecture that is suitable for high-speed operation. By employing an inverter with resistive feedback as a driver cell, the proposed driver topology can overcome the disadvantage of conventional voltage-mode drivers, namely, that the pre-driver power consumption increases as the data rate increases. This driver topology has another advantage that equalization can be easily realized. In order to evaluate the performance of the proposed driver, a PRBS generator, a serializer, and a half-rate clock generator are included in the prototype chip. The proposed driver and equalizer circuit operate reliably at a data rate of up to 20 Gb/s exhibiting an energy efficiency of 0.4 pJ/b for an output swing of 250 mVppd.
Year
DOI
Venue
2015
10.1109/ASSCC.2015.7387466
2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Keywords
Field
DocType
constant Gm,inverter,resistive feedback,transmitter,transmitter driver,transmitter equalization,voltage-mode driver
Transmitter,Clock generator,Inverter,Equalization (audio),Computer science,Efficient energy use,Driver circuit,Real-time computing,Electronic engineering,Serializer,Chip
Conference
Volume
Issue
Citations 
51
10
1
PageRank 
References 
Authors
0.36
6
9
Name
Order
Citations
PageRank
Gyu-Seob Jeong1219.00
Sang-Hyeok Chu2142.63
Yoonsoo Kim312919.27
Sungchun Jang4163.34
sungwoo kim5375.93
Woo-Rham Bae64014.93
Sung-Yong Cho7214.41
haram ju8114.11
Deog-Kyoon Jeong9626119.05