Title
Design and evaluation of Side Channel Attack resistant asynchronous AES Round Function
Abstract
A novel Asynchronous AES Round Function design is proposed in this paper, which offers increased Side-Channel Attack (SCA) resistance by combining the advantages of dual rail encoding and clock free operation. The design is based on a Delay Insensitive (DI) logic paradigm known as Null Convention Logic. By reducing switching activity and thereby Signal-to-Noise (SNR) ratio, the proposed design leaks far less side channel information than traditional approaches and this feature boosts SCA resistance of this approach. Functional verification and WASSO analysis simulations were carried out on both synchronous approach and the proposed NCL based approach using Xilinx simulation tools to validate the claims related to benefits of employing this novel dual rail design approach.
Year
DOI
Venue
2012
10.1109/MWSCAS.2012.6292044
Midwest Symposium on Circuits and Systems Conference Proceedings
Keywords
Field
DocType
formal logic,cryptography,switches,resistance,signal to noise ratio,encoding
Asynchronous communication,Functional verification,Round function,Computer science,Cryptography,Signal-to-noise ratio,Electronic engineering,Side channel attack,Asynchronous circuit,Embedded system,Encoding (memory)
Conference
ISSN
Citations 
PageRank 
1548-3746
0
0.34
References 
Authors
4
4
Name
Order
Citations
PageRank
siva pavan kumar kotipalli100.34
kyungki kim200.34
Yong-bin Kim333855.72
Minsu Choi415627.63