Name
Abstract | ||
|---|---|---|
NAND multi-level cell (MLC) flash memories are widely used due to low cost and high capacity. However the increased number of levels in MLC results in larger interference and errors. The errors in MLC flash memories tend to be asymmetric and with limited-magnitude. To take advantage of the characteristics, we propose limited-magnitude parity check codes, which can reduce errors more effectively. A key advantage of the proposed method is that it has low complexity for encoding and decoding. Another useful feature of the proposed method is that the code rate and the block size can be chosen almost continuously unlike conventional error correcting codes. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/MWSCAS.2012.6291949 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Keywords | Field | DocType |
decoding,computer architecture,interference | Block size,Parity bit,Magnitude (mathematics),Code rate,Computer science,Algorithm,Electronic engineering,NAND gate,Interference (wave propagation),Decoding methods,Computer hardware,Encoding (memory) | Conference |
ISSN | Citations | PageRank |
1548-3746 | 0 | 0.34 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Myeongwoon Jeon | 1 | 9 | 2.70 |
| Sungkyu Chung | 2 | 2 | 1.10 |
| Beom-Ju Shin | 3 | 30 | 3.94 |
| Jungwoo Lee | 4 | 1467 | 156.34 |