Name
Abstract | ||
|---|---|---|
In-Loop filtering in HEVC/H. 265 is one of most computation intensive block taking around 15-20% of overall complexity for decoding. The loop filtering in HEVC is more sophisticated with introduction of Sample adaptive offset (SAO) filter in addition to de-blocking filter in comparison to H. 264. In this paper, very high performance as well as area efficient VLSI architecture is proposed for HEVC decoder, which supports 4K@60fps for next generation Ultra HDTV at 200 MHz clock. The design can process Largest Coding Unit (LCU) of size 64x64 in less than 1200 cycles with performance directly scaling down based on LCU size. The architecture consists of LCU level pipelining across de-blocking and SAO filtering with four & three stage internal pipeline within each block. The architectures proposes fully on-the-fly filtering avoiding memory bandwidth, custom filtering order as well as scanning, 4x4 based block processing and FIFO based asynchronous architecture to achieve high performance. The final design in 28nm CMOS process is expected to take around 0.2 mm2 after actual place & route. The proposed design is capable of handling 4K@60fps as well as fully compliant to HEVC video standard specification including all corner conditions handling like slice and tiles processing via generic region definition. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ICCE-Berlin.2013.6698026 | 2013 IEEE THIRD INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - BERLIN (ICCE-BERLIN) |
Keywords | DocType | Citations |
HEVC, 4K, UHDTV, Architecture, Sample Adaptive Offset (SAO), De-blocking, Loop filter, Ultra-HD | Conference | 14 |
PageRank | References | Authors |
1.08 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mihir Mody | 1 | 43 | 10.93 |
| niraj nandan | 2 | 15 | 3.16 |
| tamama hideo | 3 | 14 | 1.08 |