| Novel Census Transform Hardware IP | 0 | 0.34 | 2021 |
| Optimal Cms System On Tda3 Processor | 0 | 0.34 | 2021 |
| Robust Digital Cluster On Jacinto6 Processor | 0 | 0.34 | 2021 |
| TileNET: Hardware accelerator for ternary Convolutional Neural Networks | 0 | 0.34 | 2021 |
| CNN Inference: Dynamic and Predictive Quantization | 0 | 0.34 | 2018 |
| Integrated Surround & CMS Automotive SoC | 0 | 0.34 | 2018 |
| End to End Learning based Self-Driving using JacintoNet | 0 | 0.34 | 2018 |
| A 216 GOPS flexible WDR Image Processor for ADAS SoC | 0 | 0.34 | 2017 |
| Optimizing Convolutional Neural Network On Dsp | 0 | 0.34 | 2016 |
| Efficient VLSI architecture for SAO decoding in 4K Ultra-HD HEVC video codec | 0 | 0.34 | 2016 |
| A Diverse Low Cost High Performance Platform for Advanced Driver Assistance System (ADAS) Applications. | 1 | 0.35 | 2016 |
| High Performance Front Camera ADAS Applications on TI's TDA3X Platform. | 0 | 0.34 | 2015 |
| Resolving ADAS imaging subsystem functional safety quagmire | 2 | 0.44 | 2015 |
| Image signal processing for front camera based automated driver assistance system | 0 | 0.34 | 2015 |
| Accelerating H.264/HEVC video slice processing using application specific instruction set processor | 0 | 0.34 | 2015 |
| High throughput VLSI architecture for HEVC SAO encoding for ultra HDTV | 5 | 0.50 | 2014 |
| A monolithic programmable Ultra-HD video codec engine | 1 | 0.40 | 2014 |
| Trends in camera based Automotive Driver Assistance Systems (ADAS) | 6 | 0.60 | 2014 |
| High Throughput Vlsi Architecture Supporting Hevc Loop Filter For Ultra Hdtv | 14 | 1.08 | 2013 |
| A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC. | 14 | 3.16 | 2012 |
