Title
An aging-aware transistor sizing tool regarding BTI and HCD degradation modes
Abstract
In this paper we present a tool based approach for an aging-aware design method. Extending the g <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> /I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sup> sizing method by operating point-dependent degradation caused by BTI and HCD enables an innovative design flow. This design flow considers performance characteristics for a fresh circuit and also those of a degraded circuit at design time. Once the degradation from a single transistor is computed, the GMID-Tool does not need any further SPICE or aging simulation. The impact of the change in design methodology is shown for a typical differential amplifier structure.
Year
DOI
Venue
2015
10.1109/MIXDES.2015.7208525
2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)
Keywords
Field
DocType
Aging-aware design,transconductance efficiency,bias temperature instability (BTI),hot carrier degradation,circuit degradation
Spice,Computer science,Electronic engineering,Design flow,Design methods,Control engineering,Degradation (geology),Sizing,Transconductance,Transistor,Differential amplifier
Conference
Citations 
PageRank 
References 
2
0.45
7
Authors
5
Name
Order
Citations
PageRank
Nico Hellwege1114.18
Nils Heidmann2143.89
marco erstling320.45
Dagmar Peters-Drolshagen43912.87
Steffen Paul514240.96