Name
Title | ||
|---|---|---|
Design Of A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic |
Abstract | ||
|---|---|---|
This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The original contribution of this paper is to evaluate, through actual chip fabrication, the potential impact of multiple-valued current-mode circuit technology on the reduction of hardware complexity required for DSP-oriented programmable ICs. The prototype FPDF fabrication with 0.6 mum CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 71%, respectively, compared with the standard binary logic implementation. |
Year | Venue | Keywords |
|---|---|---|
2003 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | multiple-valued logic, signal processor, FPGAs, FIR filters |
DocType | Volume | Issue |
Journal | E86A | 8 |
ISSN | Citations | PageRank |
0916-8508 | 2 | 0.42 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Katsuhiko Degawa | 1 | 17 | 5.30 |
| Takafumi Aoki | 2 | 915 | 125.99 |
| Tatsuo Higuchi | 3 | 302 | 68.94 |