Katsuhiko Degawa - Citegraph

Author Info

Name	Affiliation	Papers
KATSUHIKO DEGAWA	Advantest Laboratories, Ltd., 48-2 Matsubara, Kamiayashi, Aoba-ku, Sendai 989-3124, Japan	13
Collaborators	Citations	PageRank
19	17	5.30
Referers	Referees	References
35	86	46

Publications (13 rows)

Collaborators (19 rows)

Referers (35 rows)

Referees (86 rows)

Title	Citations	PageRank	Year
A new method for measuring alias-free aperture jitter in an ADC output	0	0.34	2015
An Equivalent-Time And Clocked Approach For Continuous-Time Quantization	2	0.48	2011
Phase-based alignment of two signals having partially overlapped spectra	1	0.45	2009
Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.	0	0.34	2009
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language	0	0.34	2008
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams	3	0.44	2007
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors.	0	0.34	2007
Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams.	0	0.34	2007
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors	2	0.42	2006
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors	4	0.62	2005
Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects.	0	0.34	2005
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic	3	0.44	2003
Design Of A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic	2	0.42	2003

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