Name
Title | ||
|---|---|---|
Design Optimization of On-Chip Inductive Peaking Structures for 0.13- $\mu{\hbox {m}}$ CMOS 40-Gb/s Transmitter Circuits |
Abstract | ||
|---|---|---|
This paper describes design methodologies for the optimal inductive peaking structures used for the 40-Gb/s serializing transmitter circuits presented in. The implemented transmitter had more than 400 on-chip inductors and transformers in order to achieve the bandwidth required for the 38.4-Gb/s operation demonstrated in a 0.13-μm CMOS process. A bridged T-coil network with inverted mutual couplin... |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TCSI.2009.2023772 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Design optimization,Circuits,Bandwidth,Transmitters,Inductors,CMOS technology,Design methodology,Transformers,CMOS process,Mutual coupling | Transmitter,Inductor,Electronic engineering,CMOS,Multiplexer,Bandwidth (signal processing),Electronic circuit,Current-mode logic,Parasitic extraction,Electrical engineering,Mathematics | Journal |
Volume | Issue | ISSN |
56 | 12 | 1549-8328 |
Citations | PageRank | References |
11 | 1.49 | 9 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jeong-Kyoum Kim | 1 | 33 | 4.59 |
| B.-J. Lee | 2 | 104 | 19.31 |
| Deog-Kyoon Jeong | 3 | 626 | 119.05 |