Paper Info
Title
HAMLeT Architecture for Parallel Data Reorganization in Memory
Abstract
3D-stacked integration of DRAM and logic layers using through-silicon via (TSV) technology has given rise to a new interpretation of near-data processing (NDP) concepts that were proposed decades ago. However, processing capability within the stack is limited by stringent power and thermal constraints. Simple processing mechanisms with intensive memory accesses, such as data reorganization, are an effective means of exploiting 3D stacking-based NDP. Data reorganization handled completely in memory improves the host processoru0027s memory access performance. However, in-memory data reorganization performed in parallel with host memory accesses raises issues, including interference, bandwidth allocation, and coherence. Previous work has mainly focused on performing data reorganization while blocking host accesses. This article details data reorganization performed in parallel with host memory accesses, providing mechanisms to address host/NDP interference, flexible bandwidth allocation, and in-memory coherence.
Year
DOI
Venue
2016
10.1109/MM.2015.129
IEEE Micro
Keywords
Field
DocType
DRAM chips,parallel architectures,storage management,3D stacking-based NDP,DRAM layer,HAMLeT architecture,TSV technology,dynamic random access memory,host memory access,logic layer,near-data processing,parallel data reorganization,power constraint,thermal constraint,through-silicon via technology,3D stacking,DRAM,bandwidth,data layout,memory access interference,memory access scheduling,near-data processing,parallel processing
Dram,Data processing,Computer science,Bandwidth allocation,Parallel computing,Real-time computing,Coherence (physics),Bandwidth (signal processing),Interference (wave propagation),Channel allocation schemes,AND gate
Journal
Volume
Issue
ISSN
36
1
0272-1732
Citations 
PageRank 
References 
3
0.38
6
Authors
3
Name
Order
Citations
PageRank
Berkin Akin1835.59
Franz Franchetti297488.39
James C. Hoe32048141.34