Paper Info
Title
A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip.
Abstract
Mapping constitutes a very important step in network-on-chip (NoC)-based implementation of an application. An application is often represented in the form of an application core graph. The cores of the core graph communicate between themselves using the underlying network. This paper presents a constructive heuristic to statically map applications on two-dimensional mesh-connected NoC. The approach corresponds to a design time decision of attachment of cores to the routers. The mapping results, in terms of overall communication cost metric, have been compared with many well-known techniques reported in the literature and also with an exact method built around integer linear programming (ILP). A thorough complexity analysis of the algorithm has been performed. For smaller benchmarks, the results obtained are same as those for the ILP generated solutions. For benchmarks containing 64 and higher number of cores, the mapping solutions are better than the existing ones. Dynamic performances of the mapped solutions have been compared with respect to synthetically generated self-similar traffic. In many cases, our approach requires less latency and energy per packet than the existing methods while providing higher throughput.
Year
DOI
Venue
2015
10.1142/S0218126615501261
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
Keywords
Field
DocType
Application mapping,network-on-chip,system-on-chip,intellectual property,mesh topology
Mesh networking,System on a chip,Latency (engineering),Computer science,Network packet,Parallel computing,Algorithm,Network on a chip,Electronic engineering,Integer programming,Throughput,Constructive heuristic
Journal
Volume
Issue
ISSN
24
8
0218-1266
Citations 
PageRank 
References 
5
0.42
22
Authors
4
Name
Order
Citations
PageRank
Pradip Kumar Sahu1923.87
Kanchan Manna2445.53
Tapan Shah3101.94
Santanu Chattopadhyay434344.89