Name
Abstract | ||
|---|---|---|
Testing the static performances of high-resolution analog-to-digital converters (ADCs) consumes long test times that are disproportionately high with respect to the test time devoted to other types of circuits embedded in a modern system-on-chip (SoC). In this paper, we review the state-of-the-art of reduced-code linearity test methods for pipeline ADCs and we propose a new approach that increases... |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TCSI.2015.2469014 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Pipelines,Testing,Linearity,Noise,System-on-chip,Histograms,Standards | Design for testing,Flight dynamics (spacecraft),Histogram,Linearity testing,Static testing,Computer science,Linearity,Electronic engineering,Converters,Computer hardware,Electronic circuit | Journal |
Volume | Issue | ISSN |
62 | 10 | 1549-8328 |
Citations | PageRank | References |
6 | 0.50 | 20 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Asma Laraba | 1 | 15 | 2.42 |
| Haralampos-G. D. Stratigopoulos | 2 | 252 | 28.06 |
| Salvador Mir | 3 | 426 | 56.22 |
| Herve Naudet | 4 | 9 | 1.35 |