Name
Abstract | ||
|---|---|---|
A fast-locking all-digital phase-locked loop (ADPLL) including a fast-locking unit, a multi-level bang-bang phase detector (ML-BBPD), a dynamic gain adjustment controller (DGAC), and a digitally controlled oscillator (DCO) is presented. The ML-BBPD provides multi-level outputs with different phase errors. According to the detection results of ML-BBPD, the DGAC can adjust the dynamic integral gain ... |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TCSI.2015.2477575 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Clocks,Bandwidth,Jitter,Time-frequency analysis,Delays,Phase locked loops,Tuning | Digitally controlled oscillator,Phase-locked loop,Control theory,Frequency offset,Delay-locked loop,Phase noise,Electronic engineering,CMOS,Phase detector,Jitter,Mathematics | Journal |
Volume | Issue | ISSN |
62 | 10 | 1549-8328 |
Citations | PageRank | References |
8 | 0.72 | 20 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jung-Mao Lin | 1 | 28 | 4.52 |
| Ching-Yuan Yang | 2 | 227 | 36.15 |